? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? accuracy up to 1 minute operational up to 10 khz 2 vrms, 6.81 vrms, 11.8 v l - l ,or scalable resolver outputs 2 ma rms output 16-bit resolution 8-bit/2-byte double buffered transparent latches dc-coupled reference accepts any waveform high-rel cmos d/r chip no +5 v supply required description the dr-11525 is a versatile multiplying digital-to-resolver converter. the digital input represents an angle, and the output is resolver type, sin/cos. the reference input will accept any waveform, even a saw- tooth for crt drive. because the reference is dc-coupled to the out- put, the dr-11525 can be used as: a digital-to-resolver converter using a sinusoidal reference as an input; a digital-to-sin/cos dc converter using a dc reference; a polar-to-rectangular converter using a reference input proportional to the radius vector; or a rotating cartwheel sweep generator for ppi displays using a sawtooth refer- ence. the dr-11525 is a complete digital-to-resolver (d/r) converter in one hybrid module. the dr-11525 circuit design allows for higher accuracy and reduces the output scale factor variation so that the out- put can drive displays directly. the output line-to-ground voltage can be scaled by external resistors. the dr-11525 also includes high ac and dc common-mode rejection at the reference input. applications because of its high reliability, small size and low power consumption, the hybrid dr-11525 is ideal for the most stringent and severe indus- trial and military ground or avionics applications. all units are avail- able with mil-prf-38534 processing as a standard option. among the many possible applications are computer-based systems in which digital angle information is processed, such as synchro/resolver simulators, flight trainers, flight instrumentation, fire control systems, ir, and radar and navigation systems. in addition, the dr-11525 is ideal for motor and robotic control test systems. ? 1996, 1999 data device corporation dr-11525 16-bit high frequency hybrid digital-to-resolver converter make sure the next card you purchase has...
2 data device corporation www.ddc-web.com dr-11525 g-06/05-0 figure 1. dr-11525 block diagram test point - r d/r converter high accuracy low scale factor variation resolver scaling output amplifiers transparent latch transparent latch reference conditioner digital input bits 1-8 bits 9-16 49.92 k 49.92 k 36.71 k 36.71 k 13.37 k 13.37 k 26 v reference inputs la lm ll +s +c s1 s2 s3 s4 26 v 4.4 v differential (note 1) single-ended (note 2) adjustable (note 3) bits 1-16 resolver outputs notes: 1) 26 vrms reference in = 11.8 v l-l differential output 2) 26 vrms reference in = 6.81 vrms single-ended output 3) 4.4 vrms reference in = 2 vrms single-ended output
3 data device corporation www.ddc-web.com dr-11525 g-06/05-0 introduction as shown in figure 1, the signal conversion in the dr-11525 is performed by a high-accuracy digital-to-resolver converter whose sin and cos outputs have a low scale factor variation as a function of the digital input angle. this resolver output is ampli- fied by scaling amplifiers for resolver output. the output line cur- rents can be 2 ma rms max, which is sufficient for driving r/d converters, solid-state control transformers, and displays. output power amplifiers will be required, however, for driving electro- mechanical devices such as synchros and resolvers. the reference conditioner has a differential input with high ac and dc common mode rejection, so that a reference isolation transformer will seldom be required. there are three sets of ref- erence inputs which provide three different input/output ratios. the rh- rl input provides a 0.45 ratio between the reference input and the signal output and is designed to provide 11.8 vl-l differential output for a 26 vrms reference input. the rh2-rl2 input provides a 0.52 ratio between the reference input and the signal output and is designed to provide a 6.81 vrms single- ended output for a 26 vrms reference input. the rh3-rl3 input provides a 0.91 ratio between the reference input and the signal output and is designed to provide a 2 vrms single-ended output for a 4.4 vrms reference input. series resistors can be added to accommodate higher reference levels or to reduce the output level. notes: 1) maximum reference input rh-rl = 26v +10%; rh2-rl2 = 26v +10%; rh3-rl3 = 16.4v. (2) minimum voltage output (when using scalable ref- erence input) is 1v differential or 0.5v single ended. (3) differential is line-to-line (l-l); single ended is line-to-ground (l-gnd). table 1. dr-11525 specifications apply over temperature range, power supply range, reference voltage and frequency range, and 10% harmonic distortion in the reference. parameter unit value 16 bits resolution natural binary angle, parallel positive logic cmos and ttl compatible. inputs are cmos transient protected. logic 0 = 0 to +1 v logic 1 = +2.2v to +5v 20 max to gnd (bits 1-16) 20 max to +5v (ll , lm , la ) see timing diagram (figure 2.). a digital input logic type load current reference input type frequency range standard input voltage (note 1) rh3-rl3 rh2-rl2 rh-rl input impedance single-ended: rh-gnd differential: rh to rl hz v v v k ohm k ohm resolver 2 max (tracks reference input voltage) 11.8 nominal 6.81 (single ended) 2.0 nominal (single ended) 0.5 max 0.1 max 15 max varies with input angle. ma rms vrms l-l vrms vrms % % mv analog output type output current standard output voltage (note 2) rh-rl rh2-rl2 rh3-rl3 transform. ratio tol. scale factor variation dc offset (single ended) v mamax -15 5% -18v 35+ load current -55 to +125 -40 to +85 0 to +70 -55 to +135 c c c c temperature ranges (case) operation -1 option -2 option -3 option storage physical characteristics package type size weight in.(mm) oz (g) 36-pin ddip 0.78 x 1.9 x 0.21 (19.7 x 48.1 x 5.3) 0.85 (24) 4 to 1 min. (see ordering information) 1 minute part: 1 min up to 1 khz, 1.5 min for 1 to 5 khz, and 3 min for 5 to 10 khz (guaranteed by design - tested at 5 khz) 1 max less than 20 for any digital step change minutes lsb sec three differential solid-state inputs: two for standard 26v, one programmable. dc to 10k 4.4 26 26 100 0.5% 200 0.5% +15 5% +18v 35+ load current power supplies voltage max volt. w/o damage current or impedance accuracy and dynamics output accuracy differential linearity output settling time 16 bit digital word ( ) (1 = msb, 16 = lsb) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 degrees (hex) 0 (0000) 15 (0aab) 30 (1555) 45 (2000) 60 (2aab) 75 (3666) 90 (4000) 120 (5555) 135 (6000) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 180 (8000) 240 (aaab) 270 (c000) 285 (caab) 300 (d555) 315 (e000) 330 (eaab) 345 (f555) 359 (ffff) 0 table 2. angles in degrees cross referenced to a 16-bit digital word 0
4 data device corporation www.ddc-web.com dr-11525 g-06/05-0 data changing data stable 50 ns min. 100 ns min. 50 ns min. 100 ns min. 200 ns min. 200 ns min. ll lm la data bits (9-16) bits (1-8) 200 ns min. la, lm, ll transparent = hi latched = lo figure 2b. ll ,lm ,la timing diagrams (8 bit) 200 ns min. transparent latched data 1-16 bits 50 ns min. 100 ns min. data changing data stable figure 2a. ll ,lm ,la timing diagrams (16 bit) power supply cycling power supply cycling of the ddc converter should follow the guidelines below to avoid any potential problems. strictly main- tain proper sequencing of supplies and signals per typical cmos circuit guidelines: - apply power supplies first (+15, -15v and ground). - apply digital control signals next. - apply analog signals last. the reverse sequence should be followed during power down of the circuit.
5 data device corporation www.ddc-web.com dr-11525 g-06/05-0 the reference conditioner output -r is intended for test purpos- es. for a 26 vrms nominal input to rh, rl, -r should be 5.9 vrms. the timing relationship of ll , lm , and la is shown in figure 2 as a design reference. output scaling and ref. level adjustment the dr-11525 operates like a multiplying d/a converter in that the voltage of each output line is directly proportional to the ref- erence voltage. see figure 3. the magnitude of the resistors, r', in ohms is calculated as fol- lows: *note: for rh2, rl2 and rh3, rl3: vout(single-ended) = 1/2 vout l-l . figure 4. differential resolver output figure 5. single-ended resolver output table 3. pin connection table pin pin pin name name name 13 14 15 16 17 18 19 20 21 22 23 24 nc +15v gnd -15v rh2 (6.81v) rl2 (6.81v) -r rl (11.8v) rl3 (2v) rh (11.8v) rh3 (2v) bit 14 1 2 3 4 5 6 7 8 9 10 11 12 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 25 26 27 28 29 30 31 32 33 34 35 36 bit 1 (msb) bit 15 bit 16 (lsb) lm ll la s4 (-cos) s1 (-sin) nc nc s3 (+sin) s2 (+cos) notes: 1. -r (pin 7) can be used for test purposes to detect whether a reference signal is present. see block diagram. 2. functions ll, la, and lm may be left unconnected when not used. 3. external scaling resistor pin 11 rh3 output pins (31, 32, 35, 36). 4. rh and rl (pins 10, 8) 26 v reference with differential outputs on pins 35, 36, 32, 31. 5. rh2 and rl2 (pins 5, 6) 26 v reference with single-ended output on pins 35, 36. 6. rh3 and rl3 (pins 11, 9) 4.4 v reference with single-ended outputs on pins 35, 36. figure 3. reference level adjustment 49.92k 49.92k 36.71k 36.71k 13.37k 13.37k reference inputs v (rh-rl) v (rh2-rl2) v (rh3-rl3) 8.703k 45.38k vout l-l + _ r r *changing input volt, will scale down output volt 1) 26v 2) 26v 3) 4.4v 1) 11.8v nom 2) 6.8v single ended 3) 2.0v nom output phasing and output scale factor the analog output signals have the following phasing: resolver output: s3s1 = (rh - rl)ao(1 + a( )) sin s2s4 = (rh - rl)ao(1 + a( )) cos the output amplifiers simultaneously track reference voltage fluctuations because they are proportional to (rh - rl). the transformation ratio ao is 11.8/26 for 11.8 vrms l-l output. the maximum variation in ao from all causes is 0.2%. the term a( ) represents the variation of the amplitude with the digital sig- nal input angle. a( ), which is called the scale factor variation, is a smooth function of ( ) without discontinuities and is less than 0.1% for all values of ( ). therefore, the analog output can vary as much as 0.3% due to the transformation ratio and scale fac- tor variations. because the amplitude factor (rh - rl)ao(1 + a( )) varies simultaneously on all output lines, it will not be a source of error when the dr-11525 is to drive a ratiometric system such as a synchro or resolver. however, if the outputs are used indepen- dently, as in x-y plotters, the amplitude variations must be taken into account. for rh-rl: vout l-l = 45.38k vin 100k + r' *for rh2-rl2: vout l-l = 45.38k vin 86.63k + r' *for rh3-rl3: vout l-l = 45.38k vin 49.92k + r' dr-11525 s3 s1 s2 s4 s3 s1 s2 s4 35 32 36 31 dr-11525 s3 s2 gnd s3 s2 35 (+sin) 36 (+cos) 3
6 data device corporation www.ddc-web.com dr-11525 g-06/05-0 notes: 1. dimensions shown are in inches (millimeters). 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.005 of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements of mil-std-202e, method 208c. figure 6. dr-11525 mechanical outline 36-pin ddip (ceramic) 0.210 max (5.33) 0.250 min (6.35) 0.018 0.002 dia typ (0.46 0.05) 17 eq. sp. @ 0.100 = 1.700 tol noncum (@ 2.54 = 43.18) 1.900 max (48.26) 0.800 max (20.32) 0.010 typ (0.25) side view 1 19 18 36 bottom view 0.100 typ (2.54) 0.600 (15.24) pin numbers for reference only 1.000 .010 (25.4 0.25) 0.100 0.010 typ (2.54 0.25) 0.180 10% (4.57 10%) 19 18 36 1 0.800 max (20.32) pin 1 denoted by index mark 1.900 max (48.26) 0.010 0.002 typ (0.25 0.05) pin numbers for reference only 0.018 0.002 typ (0.46 0.05) 0.100 typ (2.54) 0.020 r typ (0.51) bottom view side view notes: 1. dimensions shown are in inches (millimeters). 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.005 of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements of mil-std-202e, method 208c. figure 7. dr-11525 mechanical outline 36-pin flat pack (ceramic)
7 data device corporation www.ddc-web.com dr-11525 g-06/05-0 ordering information dr-11525d x-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above accuracy: 3 = 4 minutes + 1 lsb 4 = 2 minutes + 1 lsb 5 = 1 minute + 1 lsb* reliability: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b** 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b** with pind testing 7 = b** with solder dip 8 = b** with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55 to +125c (case) 2 = -40 to +85c (case) 3 = 0 to +70c (case) 4 = -55 to +125c (case) + variables data 5 = -40 to +85c (case) + variables data 8 = 0 to +70c (case) + variables data options: x = none package: d = dip package f = flat package * consult factory for availability of 1 minute parts. ** standard ddc processing with burn-in and full temperature test (see table below). table 1 1015 (note 1) , 1030 (note 2) burn-in notes: 1. for process requirement "b*" (refer to ordering information), devices may be non-compliant with mil- std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing for hybrid and monolithic hermetic products
the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-150012-11, fax: +49-(0)89-150012-22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com 8 g-06/05-0 printed in the u.s.a. data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u
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